1. Field of the Invention
The present invention relates to a metallization process for manufacturing semiconductor devices. More particularly, the invention relates to a method for depositing a contact barrier layer.
2. Background of the Related Art
Sub-half micron multilevel metallization represents one of the key technologies for the next generation of very large scale integration (VLSI) for integrated circuits (IC). Reliable formation of multilevel interconnect features, including contacts, vias, lines, and trenches is important to the success of VLSI and to the continued effort to increase circuit density on individual substrates and dies. As circuit densities increase, the widths of features decrease to 0.50 xcexcm or less, whereas the thickness of the dielectric layers remains substantially constant, resulting in increased aspect ratios of the features, i.e., the height divided by width. Many traditional deposition processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), are being challenged in applications where the aspect ratio of features formed on a substrate exceeds 2:1, and particularly where the aspect ratio approaches 4:1.
One difficulty in depositing a uniform metal-containing layer into high aspect ratio features arises when the metal-containing layer deposits on the sidewalls of the features and across the width of the feature to eventually converge across the width of the feature before the feature is completely filled. When the partially filled feature is covered, voids and discontinuities will form within the material deposited in the feature. These voids and discontinuities may result in unreliable electrical contacts, interconnects, and other circuit features.
One method used to reduce the likelihood that voids will form in features is to planarize the metal by annealing at high temperatures (e.g.,  greater than 350xc2x0 C.). Formation of a continuous wetting layer on the substrate is a key for successful planarization at high temperatures. However, planarization at high temperatures can result in diffusion of metals through barrier/liner layers and into surrounding dielectric materials. As a result, high temperature processes have not been used at the contact level of a substrate.
It has been discovered that a thin conformal metal film is a good wetting layer for subsequent physical vapor deposition and planarization techniques performed at low temperatures (e.g.,  less than 550xc2x0 C.). This process is more thoroughly disclosed in U.S. Pat. No. 5,877,087, Mosely et al., entitled xe2x80x9cLow Temperature Integrated Metallization Process and Apparatusxe2x80x9d which was issued on Mar. 2, 1999, and is commonly assigned to Applied Materials, Inc.
Mosely et al. teaches first depositing a thin refractory metal layer, then depositing a CVD metal layer at a low temperature to provide a conformal wetting layer for a subsequently deposited PVD metal. The PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free in the feature. The refractory metal layer provides a barrier to diffusion by the CVD or PVD metal layers into the underlying layers which are often dielectric layers which are susceptible to metal diffusion. The refractory metal layer typically includes such materials as titanium (Ti), titanium nitride, or a combination of these materials. The CVD and PVD layers have conventionally been aluminum (Al) and aluminum doped with copper. However, deposition of aluminum over an underlying titanium (Ti) refractory metal layer presents the problem of titanium tri-aluminide (TiAl3) formation. Ti has a propensity to bind Al and form TiAl3 which is an insulator, thereby compromising the performance of a conductive feature.
One solution to prevent TiAl3 formation is to follow deposition of a Ti layer with deposition of a titanium nitride (TiN) layer. The overlying TiN layer reduces the amount of Ti available to bind Al, thereby minimizing the formation of TiAl3. Additionally, the TiN layer is a good intermediate xe2x80x9cgluexe2x80x9d layer providing good bonding with both titanium and aluminum, yet titanium nitride does not interact with the aluminum. Although a deposition sequence of Ti/TiN/Al has been shown to reduce the formation of TiAl3, the sequence requires that the TiN layer substantially cover the Ti layer in order to prevent any interaction with Al. Unfortunately, the inclusion of an additional layer in the metallization stack further decreases the feature size. In an attempt to minimize the thickness of the metallization stack, a very thin layer of TiN layer has been deposited on the Ti layer. However, such a thin TiN layer may be less than continuous and thereby less effective at preventing the formation of TiAl3.
One alternative solution to avoid increased barrier layer thickness by the combination of a Ti/TiN barrier layer is to use TiN as barrier layer in the absence of an underlying Ti layer. However, a TiN barrier layer is conventionally deposited by physical vapor deposition techniques which may result in less than conformal barrier layer in the small, high aspect ratio features and thus, may be ineffective at preventing diffusion between the layers of the deposited metallization stack.
One notable problem occurs in multi-layer metallization processes where titanium and/or titanium nitride are used as a barrier layer for conducting metals such as aluminum and copper. In high temperature (e.g.,  greater than 350xc2x0 C.) processes, such as the planarization techniques described in Mosely et al., aluminum may diffuse through the Ti, combination Ti/TiN, or TiN barrier layers. If the metal is deposited at the contact level, conducting metals can diffuse through the barrier layers and react with the underlying silicon and surrounding oxides. The diffusion of Aluminum, and now copper, which is being used because of copper""s lower resistivity, higher electromigration resistance, and higher current carrying capacity compared to aluminum, into the underlying silicon and surrounding oxides can alter the electronic device characteristics of the adjacent layers and form a conductive path between the layers, thereby reducing the reliability of the overall circuit and may form short circuits which can result in device failure.
Therefore, there remains a need for a reliable barrier layer scheme for metallization processes, particularly in processes for filling and planarizing high aspect ratio sub-half micron contacts and vias with conducting metals such as aluminum and copper.
An embodiment of the invention provides a process for forming a conductive feature on a substrate. In one aspect, a thin barrier layer is formed on a substrate followed by a thin conformal metal layer deposited by chemical vapor deposition (CVD) formed over the barrier layer. The barrier layer has a thickness less than about 2000 xc3x85, and preferably between about 5 xc3x85 and 1000 xc3x85. The conformal metal layer has a thickness between about 200 xc3x85 and 1 micron, preferably a thickness less than the thickness which would seal the top of the feature. A metal layer is then deposited by physical vapor deposition over the conformal metal layer at a temperature below about 660xc2x0 C. to substantially fill the aperture. The PVD metal layer and the CVD conformal metal layer may then be annealed at a temperature between about 250xc2x0 C. and about 450xc2x0 C. The CVD conformal metal layer and the PVD metal layer are typically a metal conductor, preferably aluminum (Al), copper (Cu), and combinations thereof. The barrier/wetting layer is made of a material selected from the group of tantalum (Ta), tantalum nitride (TaNx, tungsten (W), or tungsten nitride (WNx) and combinations thereof. The process is preferably carried out sequentially in an integrated processing system.
In another aspect of the invention, a substrate is produced from the metallization process that is carried out in an integrated processing system that includes both a PVD and CVD processing chamber. The substrate comprises a semiconductor substrate, a dielectric layer formed on the semiconductor substrate, the dielectric layer having an aperture formed therein and communicating with the semiconductor substrate, a barrier/wetting layer formed over the surfaces of the aperture, wherein the barrier/wetting layer comprises a material selected from the group of Ta, TaNx, W, WNx, and combinations thereof. The barrier layer preferably has a thickness less than about 2000 xc3x85, preferably between about 5 xc3x85 and 1000 xc3x85. Next, a chemical vapor deposited conformal metal layer such as Al, Cu, and combinations thereof is formed over the barrier/wetting layer. Finally, a metal layer is deposited by physical vapor deposition or electroplating over the chemical vapor deposited conformal metal layer. The physical vapor deposited metal layer is deposited at a temperature below about 400xc2x0 C. to cause the CVD and PVD deposited metal layers to flow into the aperture and form an interconnect without forming voids therein. The PVD metal layer preferably comprises a material selected from the group of Al, Cu, and combinations thereof.
Another aspect of the invention provides for a program product, which when read and executed by a computer, comprises the steps of generating a plasma in a chamber, providing a bias to a target disposed in the chamber, providing a bias to a coil, and maintaining the chamber pressure between about 0.5 mTorr and about 100 mTorr during the deposition of a material onto a substrate. The program product provides a RF bias to the coil between about 200 W and about 24 kW, and provides a bias to the target between about 200 W and about 24 kW. The program product may further comprise providing a bias to the substrate of between about 0 W and 1000 W. The target disposed in the chamber is preferably a material selected from the group of Ta, TaN, W, WN, and combinations thereof.